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general description the max9311/max9313 are low-skew, 1-to-10 differen- tial drivers designed for clock and data distribution. these devices allow selection between two inputs. the selected input is reproduced at 10 differential outputs. the differential inputs can be adapted to accept single- ended inputs by connecting the on-chip v bb supply to one input as a reference voltage. the max9311/max9313 feature low part-to-part skew (30ps) and output-to-output skew (12ps), making them ideal for clock and data distribution across a backplane or a board. for interfacing to differential hstl and lvpecl signals, these devices operate over a +2.25v to +3.8v supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5v or +3.3v supply. for differential lvecl operation, these devices operate from a -2.25v to -3.8v supply. the max9311 features an on-chip v bb reference output of 1.425v below the positive supply voltage. the max9313 offers an on-chip v bb reference output of 1.32v below the positive supply voltage. both devices are offered in space-saving, 32-pin 5mm ? 5mm tqfp, 5mm x 5mm qfn, and industry-standard 32-pin 7mm x 7mm lqfp packages. applications precision clock distribution low-jitter data repeater features +2.25v to +3.8v differential hstl/lvpecl operation -2.25v to -3.8v lvecl operation 30ps (typ) part-to-part skew 12ps (typ) output-to-output skew 312ps (typ) propagation delay 300mv differential output at 3ghz on-chip reference for single-ended inputs output low with open input pin compatible with mc100lvep111 (max9311) and mc100ep111 (max9313) offered in tiny qfn* package (70% smaller footprint than lqfp) max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers ________________________________________________________________ maxim integrated products 1 top view 32 28 29 30 31 25 26 27 v cc q1 q0 v cc q2 10 13 15 14 16 11 12 9 17 18 19 20 21 22 23 24 q3 q4 q5 q6 v ee v bb clk0 clksel 2 3 4 5 6 7 8 1 v cc max9311 max9313 q0 q1 q2 q3 q4 q5 q6 v cc q8 q9 v cc q7 q9 q8 q7 clk1 clk1 clk0 lqfp (7mm 7mm), tqfp (5mm 5mm), qfn (no leads extending from qfn package) clksel 0 1 max9311/max9313 on off off on clk0, clk0 clk1, clk1 pin configuration ordering information 19-2078; rev 2; 10/02 part temp. range pin-package max9311 ecj -40 c to +85 c 32 lqfp (7mm ? 7mm) max9311egj* -40 c to +85 c 32 qfn (5mm ? 5mm) max9311ehj* -40 c to +85 c 32 tqfp (5mm ? 5mm) max9313 ecj -40 c to +85 c 32 lqfp (7mm ? 7mm) max9313egj* -40 c to +85 c 32 qfn (5mm ? 5mm) max9313ehj* -40 c to +85 c 32 tqfp (5mm ? 5mm) for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. *future product?ontact factory for availability.
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc - v ee = +2.25v to +3.8v, outputs loaded with 50 ? ?% to v cc - 2v, clksel = high or low, unless otherwise noted.) (notes 1?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc - v ee ...............................................................................4.1v inputs (clk_, clk_ , clksel)..............v ee - 0.3v to v cc + 0.3v clk_ to clk_ ....................................................................?.0v continuous output current .................................................50ma surge output current........................................................100ma v bb sink/source current ...............................................?.65ma junction-to-ambient thermal resistance in still air 7mm x 7mm lqfp .....................................................+90?/w junction-to-ambient thermal resistance with 500 lfpm airflow 7mm x 7mm lqfp .....................................................+60?/w junction-to-case thermal resistance 7mm x 7mm lqfp .....................................................+12?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? esd protection human body model (clksel, clk_, clk_ , q_, q_, v bb ).......................................................................2kv soldering temperature (10s) ...........................................+300? -40? +25? +85? parameter symbol conditions min max min max min max units single-ended input (clksel) m ax 9311 v cc - 1.23 v cc v cc - 1.23 v cc v cc - 1.23 v cc input high voltage v ih inter nal v b b thr eshol d m ax 9313 v cc - 1.165 v cc v cc - 1.165 v cc v cc - 1.165 v cc v m ax 9311 v ee v cc - 1.62 v ee v cc - 1.62 v ee v cc - 1.62 input low voltage v il inter nal v b b thr eshol d m ax 9313 v ee v cc - 1.475 v ee v cc - 1.475 v ee v cc - 1.475 v input high current i ih 150 150 150 a input low current i il -10 +10 -10 +10 -10 +10 a differential inputs (clk_, clk_ ) m ax 9311 v cc - 1.23 v cc v cc - 1.23 v cc v cc - 1.23 v cc single-ended input high voltage v ih v bb connected to clk_ ( v il for v bb connected to c lk_) , figure 1 m ax 9313 v cc - 1.165 v cc v cc - 1.165 v cc v cc - 1.165 v cc v
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc - v ee = +2.25v to +3.8v, outputs loaded with 50 ? 1% to v cc - 2v, clksel = high or low, unless otherwise noted.) (notes 1 4) -40 c +25 c +85 c parameter symbol conditions min max min max min max units m ax 9311 v ee v cc - 1.62 v ee v cc - 1.62 v ee v cc -1.62 single-ended input low voltage v il v bb connected to clk_ ( v ih for v bb connected to c lk_) , figure 1 m ax 9313 v ee v cc - 1.475 v ee v cc - 1.475 v ee v cc -1.475 v high voltage of differential input v ihd v ee +1.2 v cc v ee + 1.2 v cc v ee +1.2 v cc v low voltage of differential input v ild v ee v cc - 0.095 v ee v cc - 0.095 v ee v cc - 0.095 v for v cc - v ee < 3.0v 0.095 v cc - v ee 0.095 v cc - v ee 0.095 v cc - v ee differential input voltage v ihd - v ild for v cc - v ee 3.0v 0.095 3.0 0.095 3.0 0.095 3.0 v input high current i ih 150 150 150 a clk_ input low current i ilclk -10 +10 -10 +10 -10 +10 a clk_ input low current i ilclk -150 -150 -150 a outputs (q_, q _ ) single-ended output high voltage v oh figure 1 v cc - 1.025 v cc - 0.900 v cc - 1.025 v cc - 0.900 v cc - 1.025 v cc - 0.900 v single-ended output low voltage v ol figure 1 v cc - 1.93 v cc - 1.695 v cc - 1.93 v cc - 1.695 v cc - 1.93 v cc - 1.695 v differential output voltage v oh - v ol figure 1 670 950 670 950 670 950 mv reference (v bb ) m ax 9311 v c c - 1.525 v c c - 1.325 v c c - 1.525 v c c - 1.325 v c c - 1.525 v c c - 1.325 reference voltage output (note 5) v bb i bb = 0.5ma m ax 9313 v cc - 1.38 v cc - 1.26 v cc - 1.38 v cc - 1.26 v cc - 1.38 v cc - 1.26 v power supply supply current (note 6) i ee 75 82 95 ma
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers 4 _______________________________________________________________________________________ ac electrical characteristics (v cc - v ee = 2.25v to 3.8v, outputs loaded with 50 ? 1% to v cc - 2v, input frequency = 1.5ghz, input transition time = 125ps (20% to 80%), clksel = high or low, v ihd = v ee + 1.2v to v cc , v ild = v ee to v cc - 0.15v, v ihd - v ild = 0.15v to the smaller of 3v or v cc - v ee , unless otherwise noted. typical values are at v cc - v ee = 3.3v, v ihd = v cc -1v, v ild = v cc -1.5v.) (note 7) -40 c +25 c +85 c parameter symbol conditions min typ max min typ ma min typ max units differential input-to- output delay t plhd , t phld figure 2 220 321 380 220 312 410 260 322 400 ps output-to- output skew (note 8) t skoo 12 46 12 46 10 35 ps part-to-part skew (note 9) t skpp 30 160 30 190 30 140 ps f in = 1.5gh z, c l ock p atter n 1.2 2.5 1.2 2.5 1.2 2.5 added random jitter (note 10) t rj f in = 3.0gh z, c l ock p atter n 1.2 2.6 1.2 2.6 1.2 2.6 ps (rms) added deterministic jitter (note 10) t dj 3gbps, 2 23 -1 prbs pattern 80 95 80 95 80 95 ps (p-p) v oh - v ol 350mv, clock pattern, figure 2 2.0 2.0 3.0 2.0 switching frequency f max v oh - v ol 500mv, clock pattern, figure 2 1.5 1.5 1.5 ghz output rise/fall time (20% to 80%) t r , t f figure 2 100 112 140 100 116 140 100 121 140 ps note 1: measurements are made with the device in thermal equilibrium. note 2: current into a pin is defined as positive. current out of a pin is defined as negative. note 3: single-ended input operation using v bb is limited to v cc - v ee = 3.0v to 3.8v for the max9311 and v cc - v ee = 2.7v to 3.8v for the max9313. note 4: dc parameters production tested at t a = +25 c. guaranteed by design and characterization over the full operating temper- ature range. note 5: use v bb only for inputs that are on the same device as the v bb reference. note 6: all pins open except v cc and v ee . note 7: guaranteed by design and characterization. limits are set at 6 sigma. note 8: measured between outputs of the same part at the signal crossing points for a same-edge transition. note 9: measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. note 10: device jitter added to the input signal.
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers _______________________________________________________________________________________ 5 typical operating characteristics (v cc = +3.3v, v ee = 0, v ihd = v cc - 0.95v, v ild = v cc - 1.25v, input transition time = 125ps (20% to 80%), f in = 1.5ghz, outputs loaded with 50 ? to v cc - 2v, t a = +25 c, unless otherwise noted.) 50 60 55 70 65 80 75 85 -40 10 -15 35 60 85 supply current (i ee ) vs. temperature max9311 toc01 temperature ( c) supply current (ma) 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1000 2000 3000 output amplitude (v oh - v ol ) vs. frequency max9311 toc02 frequency (mhz) output amplitude (v) 0.1 100 130 -40 -15 10 35 60 85 transition time vs. temperature max9311 toc03 temperature ( c) transition time (ps) 105 110 115 120 125 t r t f 303 305 304 307 306 309 308 310 312 311 313 1.0 3.8 propagation delay vs. high voltage of differential input (v ihd ) max9311 toc04 v ihd (v) propagation delay (ps) 1.4 1.8 2.2 3.4 3.0 2.6 t plhd t phld v ihd - v ild = 150mv 200 220 240 260 280 300 320 340 360 -40 -15 10 35 60 85 propagation delay vs. temperature max9311 toc05 temperature ( c) propagation delay (ps) v ihd = v cc - 0.95v v ild = v cc - 1.1v t plhd t phld
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers 6 _______________________________________________________________________________________ pin description pin name function 1, 9, 16, 25, 32 v cc positive supply voltage. bypass from v cc to v ee with 0.1f and 0.01f ceramic capacitors. place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 clksel clock select input (single-ended). drive low to select the clk0, clk0 input. drive high to select the clk1, clk1 input. the clksel threshold is v bb . if clksel is not driven by a logic signal, use a 1k ? pulldown to v ee to select clk0, clk0 , or a 1k ? pullup to v cc to select clk1, clk1 . 3 clk0 noninverting differential clock input 0. internal 75k ? pulldown resistor. 4 clk0 inverting differential clock input 0. internal 75k ? pullup and pulldown resistors. 5v bb refer ence outp ut v ol tag e. c onnect to the i nver ti ng or noni nver ti ng cl ock i np ut to p r ovi d e a r efer ence for si ng l e- end ed op er ati on. w hen used , b yp ass w i th a 0.01f cer am i c cap aci tor to v c c ; other w i se, l eave op en. 6 clk1 noninverting differential clock input 1. internal 75k ? pulldown resistor. 7 clk1 inverting differential clock input 1. internal 75k ? pullup and pulldown resistors. 8v ee negative supply voltage 10 q9 inverting q9 output. typically terminate with 50 ? resistor to v cc - 2v. 11 q9 noninverting q9 output. typically terminate with 50 ? resistor to v cc - 2v. 12 q8 inverting q8 output. typically terminate with 50 ? resistor to v cc - 2v. 13 q8 noninverting q8 output. typically terminate with 50 ? resistor to v cc - 2v. 14 q7 inverting q7 output. typically terminate with 50 ? resistor to v cc - 2v. 15 q7 noninverting q7 output. typically terminate with 50 ? resistor to v cc - 2v. 17 q6 inverting q6 output. typically terminate with 50 ? resistor to v cc - 2v. 18 q6 noninverting q6 output. typically terminate with 50 ? resistor to v cc - 2v. 19 q5 inverting q5 output. typically terminate with 50 ? resistor to v cc - 2v. 20 q5 noninverting q5 output. typically terminate with 50 ? resistor to v cc - 2v. 21 q4 inverting q4 output. typically terminate with 50 ? resistor to v cc - 2v. 22 q4 noninverting q4 output. typically terminate with 50 ? resistor to v cc - 2v. 23 q3 inverting q3 output. typically terminate with 50 ? resistor to v cc - 2v. 24 q3 noninverting q3 output. typically terminate with 50 ? resistor to v cc - 2v. 26 q2 inverting q2 output. typically terminate with 50 ? resistor to v cc - 2v. 27 q2 noninverting q2 output. typically terminate with 50 ? resistor to v cc - 2v. 28 q1 inverting q1 output. typically terminate with 50 ? resistor to v cc - 2v. 29 q1 noninverting q1 output. typically terminate with 50 ? resistor to v cc - 2v. 30 q0 inverting q0 output. typically terminate with 50 ? resistor to v cc - 2v. 31 q0 noninverting q0 output. typically terminate with 50 ? resistor to v cc - 2v.
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers _______________________________________________________________________________________ 7 detailed description the max9311/max9313 are low skew, 1-to-10 differen- tial drivers designed for clock and data distribution. a 2:1 mux selects between the two differential inputs, clk0, clk0 and clk1, clk1 . the 2:1 mux is switched by the single-ended clksel input. a logic low selects the clk0, clk0 input. a logic high selects the clk1, clk1 input. the logic threshold for clksel is set by an internal v bb voltage reference. the clksel input can be driven to v cc and v ee or by a single-ended lvpecl/ lvecl signal. the selected input is reproduced at 10 differential outputs. for interfacing to differential hstl and lvpecl signals, these devices operate over a +2.25v to +3.8v supply range, allowing high-performance clock or data distribu- tion in systems with a nominal +2.5v or +3.3v supply. for differential lvecl operation, these devices operate from a -2.25v to -3.8v supply. the differential inputs can be configured to accept sin- gle-ended inputs when operating at approximately v cc - v ee = +3.0v to +3.8v for the max9311 or v cc - v ee = +2.7v to +3.8v for the max9313. this is accomplished by connecting the on-chip reference voltage, v bb , to an input as a reference. for example, the differential clk0, clk0 input is converted to a noninverting, single-ended input by connecting v bb to clk0 and connecting the single-ended input to clk0. similarly, an inverting input is obtained by connecting v bb to clk0 and connecting the single-ended input to clk0 . with a differential input configured as single-ended (using v bb ), the single- ended input can be driven to v cc and v ee or with a sin- gle-ended lvpecl/lvecl signal. when a differential input is configured as a single-ended input (using v bb ), the approximate supply range is v cc - v ee = +3.0v to +3.8v for the max9311 and v cc - v ee = +2.7v to +3.8v for the max9313. this is because one of the inputs must be v ee + 1.2v or higher for proper oper- ation of the input stage. v bb must be at least v ee + 1.2v because it becomes the high-level input when the other (single-ended) input swings below it. therefore, mini- mum v bb = v ee + 1.2v. the minimum v bb output for the max9311 is v cc - 1.525v and the minimum v bb output for the max9313 is v cc - 1.38v. substituting the minimum v bb output for each device into v bb = v ee + 1.2v results in a minimum supply of 2.725v for the max9311 and 2.58v for the max9313. rounding up to standard supplies gives the single-ended operating supply ranges of v cc - v ee = 3.0v to 3.8v for the max9311 and v cc - v ee = 2.7v to 3.8v for the max9313. when using the v bb reference output, bypass it with a 0.01f ceramic capacitor to v cc . if the v bb reference is not used, it can be left open. the v bb reference can source or sink 0.5ma, which is sufficient to drive two inputs. use v bb only for inputs that are on the same device as the v bb reference. the maximum magnitude of the differential input from clk_ to clk_ is 3.0v or v cc - v ee , whichever is less. this limit also applies to the difference between any ref- erence voltage input and a single-ended input. the differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. the inverting inputs ( clk0 and clk1 ) are biased with a 75k ? pullup to v cc and a 75k ? pulldown to v ee . the noninverting inputs (clk0 and clk1) are biased with a 75k ? pulldown to v ee . the single-ended clksel input does not have a bias resistor. if not driven, pull clksel up or down with a 1khz resistor (see pin description ). specifications for the high and low voltages of a differen- tial input (v ihd and v ild ) and the differential input volt- age (v ihd - v ild ) apply simultaneously (v ild cannot be higher than v ihd ). output levels are referenced to v cc and are considered lvpecl or lvecl, depending on the level of the v cc supply. with v cc connected to a positive supply and v ee connected to gnd, the outputs are lvpecl. the outputs are lvecl when v cc is connected to gnd and v ee is connected to a negative supply. a single-ended input of at least v bb 95mv or a differen- tial input of at least 95mv switches the outputs to the v oh and v ol levels specified in the dc electrical characteristics table. applications information supply bypassing bypass v cc to v ee with high-frequency surface-mount ceramic 0.1f and 0.01f capacitors in parallel as close to the device as possible, with the 0.01f value capaci- tor closest to the device. use multiple parallel vias for low inductance. when using the v bb reference output, bypass it with a 0.01f ceramic capacitor to v cc (if the v bb reference is not used, it can be left open). traces input and output trace characteristics affect the perfor- mance of the max9311/max9313. connect each signal of a differential input or output to a 50 ? characteristic impedance trace. minimize the number of vias to prevent impedance discontinuities. reduce reflections by main- taining the 50 ? characteristic impedance through con- nectors and across cables. reduce skew within a
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers 8 _______________________________________________________________________________________ differential pair by matching the electrical length of the traces. output termination terminate outputs through 50 ? to v cc - 2v or use an equivalent thevenin termination. when a single-ended signal is taken from a differential output, terminate both outputs. for example, if q0 is used as a single-ended output, terminate both q0 and q0 . chip information transistor count: 250 v il v ih v oh - v ol v oh v ol q_ q_ clk_ clk_ (connected to clk_ ) v bb figure 1. switching with single-ended input 0 (differential) 80% 20% 80% 20% 0 (differential) v oh - v ol v ihd - v ild v ihd v ild q_ q_ (q_) - (q_) clk_ clk_ t plhd t phld t r t f v oh v ol figure 2. differential transition time and propagation delay timing diagram
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers _______________________________________________________________________________________ 9 q0 clk0 0 1 v cc 75k ? 75k ? 75k ? q0 q2 q2 q3 q3 q4 q4 q5 q5 q6 q6 q7 q7 q8 q8 q9 q9 q1 q1 clk0 clk1 clksel v cc 75k ? 75k ? 75k ? clk1 v ee v ee v ee v ee v bb functional diagram
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers 10 ______________________________________________________________________________________ 32l/48l tqfp eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers ______________________________________________________________________________________ 11 32l tqfp, 5x5x01.0.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max9311/max9313 1:10 differential lvpecl/lvecl/hstl clock and data drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. 32l qfn.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max9313 part number table notes: see the max9313 quickview data sheet for further information on this product family or download the max9313 full data sheet (pdf, 384kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max9313ec j lqfp;32 pin;7x7x1.4 mm dwg: 21-0054f (pdf) use pkgcode/variation: c 32-1 * rohs/lead-free: no materials analysis max9313ec j-t rohs/lead-free: no max9313egj qfn;32 pin;5x5x0.9mm dwg: 21-0091i (pdf) use pkgcode/variation: g3255-1 * -40c to +85c rohs/lead-free: no materials analysis max9313egj-t qfn;32 pin;5x5x0.9mm dwg: 21-0091i (pdf) use pkgcode/variation: g3255-1 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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